A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. The design of an integrated circuit transforms a circuit description into a geometric description called a layout. The process of converting specifications of an integrated circuit into a layout is called the physical design.
Chip designers often use electronic design automation (EDA) software tools to assist in the design process. Chip design using EDA software tools generally involves an iterative process whereby the chip design is gradually perfected. A top-down design methodology is commonly employed using hardware description languages (HDLs), such as Verilog or VHDL for example, by which the designer creates an integrated circuit by hierarchically defining functional components of the circuit, and then decomposing each component into smaller and smaller components.
The various components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. From the HDL or other high level description, the actual logic cell implementation is typically determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation. The logic cells are then “placed” (e.g., given specific coordinate locations in the circuit layout) and “routed” (e.g., wired or connected together according to the designer's circuit definitions). The placement and routing software routines generally accept as their input a flattened netlist that has been generated by the logic synthesis process. This flattened netlist identifies the specific logic cell instances from a target standard cell library, and describes the specific cell-to-cell connectivity.
In the area of custom designs, the user can directly and interactively conduct placement and routing in a manual approach, e.g., by manually manipulating the location of objects. In addition, after an initial placement/routing process that may have undergone either auto-placement or interactive placement, the layout may still undergo additional interactive changes to the existing placement of objects, by potentially inserting or moving objects in portions of the layout.
Modern designs are becoming ever more complicated with huge numbers of objects and components that must be placed on a layout, combined with the issue of making sure the placement of the large number of objects/components do not get placed in configurations that will cause design rule violations or otherwise create performance problems. The problem is that with the huge number of design decisions that must be made by a designer for these complex circuit designs, it is becoming more and more difficult to achieve an acceptable design within a reasonable amount of time and resources. As integrated circuit manufacturing technology advances, greater complexities and more required resources are needed to design on each new process. Moving from one process node to the next can be anywhere from 2×-4× hit in productivity.
Advances in EDA tools to close this gap achieve the most success when mundane tasks can be automated. When automating tasks in EDA tools, tool makers commonly implement ‘one size fits all’ solutions based upon heuristics and/or provide user-controlled options to control the design process. However, heuristics are error-prone and an explosion of options makes their controls relatively unusable to users. Therefore, conventional tools either (a) burden the user by requiring the user to explicitly set options, provide descriptions, or write code to achieve the automation needed, or (b) follow heuristics that in many cases do not satisfy even a majority of users.
Previous attempts to improve productivity in custom semiconductor layout, especially analog layout, have relied on the user performing additional work to somehow abstract key concepts (e.g., Modgen scripts, Constraints, higher-level PCells) in the creation of key layout blocks. While these techniques may achieve an acceptable design, they often require layout designers to perform work above and beyond just the creation of layout, which is the main skill comfort area for such layout designers.
Therefore, there is a need for an improved approach to implement placement to address at least the aforementioned shortfalls of conventional approaches.